About me

I'm a third year undergraduate in electronics and communication engineering at IIT Roorkee with interest in computer architecture, heterogeneous computing and FPGA based accelerators. My résumé is available here.


I have worked in past on energy estimation of DDR3 DRAMs, FPGA based FIB lookups in Named Data Network and several hobby projects hosted at my GitHub profile.

An open-source DRAM power model based on extensive experimental characterization..

Paper GitHub
Trianglify poster

Trianglify is an Android library that helps creates views with beautiful patterns. Trianglify is based on MVP architecture and licensed under MIT license.

GooglePlay Demo GitHub

pine tree Hassle free .gitignore manager.


Basic implementation of a 32-bit single core unpipelined RISC processor written in Verilog. This is a hobby project to understand how processors and operating systems work.



D. Saxena, Suyash Mahar, V. Raychoudhury, J. Cao
Scalable, High-speed On-chip-based NDN Name Forwarding using FPGA
Proceedings of the 20th International Conference on Distributed Computing and Networking (ICDCN'19), January 4-7, 2019, Bangalore, 2019

Technical Reports

Sumit Kumar Yadav, Suyash Mahar, Naveen Kakarla
Reducing DRAM Power Consumption by Exploring and Modeling Memory Access Scheduling Policies
Poster, ECE Undergraduate research symposium, July 27, 2018
Sidharth Thomas, Suyash Mahar
Implementation of CORDIC Algorithms in FPGA
Short-term project, Summer 2017 - May 2, 2017 to May 28, 2017

Fun stuff around the web

Python like STL container printing in C++
Convert C-gibberrish to English and back

Contact info

email contact@suyashmahar.me
email github/suyashmahar
location F-159, Ravindra Bhawan
IIT Roorkee